1. Field of the Invention
The present invention relates generally to the field of semiconductor devices and manufacturing methods thereof, and more particularly to the semiconductor devices with metal gates where epitaxial layers are disposed under the metal gates.
2. Description of the Prior Art
With the increasing miniaturization of semiconductor devices, various multi-gate MOSFET devices have been developed. The multi-gate MOSFETs are advantageous for the following reasons. First, the manufacturing processes of the multi-gate MOSFET devices can be easily integrated into the processes for fabricating conventional logic device processes. In addition, since the three-dimensional structure of a multi-gate MOSFET increases the overlapping area between the gate and the substrate, its channel region can be controlled more effectively. Therefore, some of the problems, such as drain-induced barrier lowering (DIBL) and short channel effect (SCE), that often occurs in small-sized planar MOSFETs can be resolved effectively by adopting multi-gate MOSFETs. Moreover, the channel width of the multi-gate MOSFET is much wider than that of the planar MOSFET. As a result, the electric current between source/drain regions of the MOSFET may be increased. However, charge carrier mobility of the channel regions is still not high enough for the multi-gate MOSFETs.